What is Arc Mapping?
Arc Mapping refers to the process of determining the interconnection pattern between Processing Elements (PEs) in an array processor based on the arcs in a data dependence graph. The arcs in this context describe dependencies between operations, and the goal is to establish the connections and delays required for efficient array processor operation. Here are the key points related to Arc Mapping:
Purpose of Arc Mapping
It is essential for determining the interconnection pattern between PEs in an array processor. It is used to understand the dependencies between operations and to establish the necessary interconnections and delays.
Manual and Systematic Approach
While arc mapping can be done manually for simple data-dependence graphs, a systematic approach is preferred for more complex operations. A systematic approach helps avoid errors and ensures accuracy in determining interconnections and delays.
Interconnection Determination
The result of arc mapping is the determination of the interconnections (represented as e’) in the array processor corresponding to a given dependence (e) in the data dependence graph. The interconnections are crucial for coordinating the flow of data between PEs.
Delay Determination
Along with interconnections, arc mapping also determines the number of delays (represented as D(e’)) required in the interconnection (e’). Delays are essential to account for dependencies between PEs that operate in parallel, such as in a pipeline structure.
Matrix Operation for Mapping
The arc mapping process involves a matrix operation utilizing a simple matrix-vector multiplication. The matrix operation includes the normal vector of hyperplanes (S) and the node mapping matrix (H).
In summary, arc mapping is a critical step in designing and configuring the interconnection pattern in an array processor based on dependencies between operations, and it involves systematic procedures to ensure accuracy, especially in complex scenarios.
Related Posts
Analog and Memory Layout Design Forum |
Physical Layout Design Forum |
RTL & Verilog Design Forum |
Semiconductor Forum |
Analog Layout Design Interview Questions | Memory Design Interview Questions |
Physical Design Interview Questions | Verilog Interview Questions |
Digital Design Interview Questions | STA Interview Questions |