Digital CMOS Abbreviation G Alphabet Dictionary
One of the four terminals of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). It is the control terminal of the transistor, represented by the metal or polysilicon plate of the MOS capacitor. The gate exhibits zero steady-state gate current but may have leakage in modern technologies.
The total area occupied by a logic gate in a semiconductor chip layout. This area ideally corresponds to the gate’s layout area and may be used in comparative studies or analyses. However, it is a small fraction of the overall layout area.
Gate Capacitance (MOSFET)
The capacitance associated with the gate of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). It exists across the oxide layer and can be between the gate and the channel when the transistor is on or between the gate and the body when the transistor is in a cutoff state.
GDS II (Graphical Database System II)
A standard file format is used for communicating layout information to vendors. It is essential for mask extraction during semiconductor chip manufacturing. GDS II files are in plain text format and primarily describe the vertices of polygons in various layers of the chip layout.
A state in a full adder where the carry-out is always true, regardless of the value of the carry-in. This state can be deduced solely from the operands, allowing all generates for all bit positions to be calculated in parallel at the start of an operation. Together with propagate, generate is used to conceptualize full adders and design fast adders efficiently.
A constant that can be declared within the entity declaration in VHDL rather than within the architecture. Generics remain unspecified until the entity is instantiated. They are powerful for creating highly scalable and modifiable code, centralizing constants, and enhancing code readability.
Generic Map (VHDL)
Part of a component instantiation in VHDL where a generic is assigned a constant value. It allows you to specify the value of a generic for a particular instance. If a generic map is not used, the default value of the generic is employed. Generic maps can be used to map generics to higher-level generics or constants.
A wire within an integrated circuit (IC) that connects widely spaced subsystems on the IC die. Global wires, especially in advanced technologies, can suffer from significant delays due to the poor scaling of resistance and routing challenges. They are often routed in higher metal layers with thicker and wider conductors to mitigate these issues.
Random logic is used to connect or interface large subsystems within a semiconductor chip. The presence of glue logic may indicate that subsystem interfaces were not adequately designed or that the overall system partitioning was not well-considered. While glue logic serves a necessary purpose, it is generally undesirable because modifications to subsystems often require a significant redesign of the glue logic.
The correct and expected output from a circuit or unit under test. The gold standard serves as a reference for comparing and evaluating the results of testing. Typically, the gold standard is obtained from a higher-level simulation that is bit-accurate.
Good Design Practices
A set of recommended practices for designers to follow during the design process. While they are generally optional, adhering to good design practices can lead to more predictable and reliable results in chip design. These practices aim to produce code that is aware of the hardware into which it will be translated.
A phenomenon observed when the ground voltage (reference voltage) of a microchip temporarily rises significantly. Ground bounce occurs due to inductance, primarily at the pad, pin, and PCB levels. High-frequency changes in currents can induce ground bounce, which can potentially trigger latch-up and affect circuit operation.
In the context of adders, it refers to a bit that indicates that a carry is generated somewhere within a continuous range of bit positions and propagates to the output of that range. Group generation is essential for designing high-speed adders.
Also related to adders, it signifies whether all bit positions within a continuous range are propagating, allowing an input carry to bypass the entire range. Group propagation, together with group generation, plays a crucial role in designing fast adders.