Digital CMOS Abbreviation JKL Alphabet Dictionary

Digital CMOS

JTAG (Joint Test Action Group)

An IEEE standard for boundary scan testing. JTAG defines test ports, sequences, and durations used in boundary scan techniques to test and debug integrated circuits.

Junction Capacitance

The built-in capacitance that forms in PN junctions when they are in equilibrium or reverse bias. The depletion region between the N and P regions acts as an insulator, and the width of this region varies with applied voltage, making junction capacitance nonlinear.

KoggeStone Adder

A type of parallel prefix adder (PPA) is used in digital circuit design. It combines generates and propagates signals progressively to resolve all bit positions. Kogge-Stone adders offer low delay, but they require many dot operators and can pose routing challenges.

Lambda-based Rules

Design rules are expressed in terms of a constant, lambda, which corresponds to half the minimum channel length. Lambda-based rules are scalable and portable across different technologies and vendors but tend to be conservative, leading to larger designs.


A sequential circuit with a level-active enable signal. The output of a latch is transparent to the input for a specific level of the clock signal and stores the input value for the opposite clock level. Latches can be used in high-performance pipelines but complicate placement and routing.

Latch-based Sense Amplifier

A type of sense amplifier used in dynamic random-access memory (DRAM) that consists of a pair of inverters connected in positive feedback. It amplifies voltage swings and is differential in nature, often requiring the use of dummy cells.

Latch Loop

A hardware section in a digital circuit that contains combinational logic blocks between latches of opposite types. Latch loops can offer high performance due to slack borrowing but can complicate placement and routing.


A dangerous phenomenon in CMOS circuits where the parasitic bipolar structure starts to conduct current, leading to positive feedback and increasing current flow between the supply and ground. Latch-up can result in catastrophic circuit failure and must be prevented by adding appropriate contacts and isolating structures.


The top-view representation of an ASIC design is often color-coded. It represents the physical arrangement of components and interconnections. The photomasks used in the fabrication process are derived from the layout.

Layout versus Schematic (LVS)

An essential step in ASIC design where the physical layout is scanned to extract its corresponding schematic representation. This extracted schematic is then compared to the original schematic from the netlist to ensure functional congruency in the fabricated chip.


Refers to all currents in a MOSFET other than the on-drift current that flows between the source and drain when the transistor is in a strong inversion state. Leakage currents can be continuous or occasional and contribute to increased power consumption and dynamic node depletion.

Level Converter

Part of the pad interface circuitry in integrated circuits. It is responsible for converting logic voltage levels between those observed in the external PCB and those used in the core of the chip.

Library (FPGA)

A collection of possible reconfigurations for a logic cell in a Field-Programmable Gate Array (FPGA). Each library entry includes the programming information, logic representation, and delay model for a specific configuration of the cell.

Linear Feedback Shift Register

A shift register where the input is a linear combination of its current output and internal signals. Linear Feedback Shift Registers have properties useful for generating pseudorandom sequences with low autocorrelation.

Linear, Triode, Ohmic Region

A region of operation for a MOSFET where current is determined by the gate, drain, and source potentials. In this region, the MOSFET behaves as a nonlinear resistor due to factors like velocity saturation and channel narrowing.


A resistor or active load in a digital gate that is not directly influenced by the gate’s inputs. It can either pull the gate’s output up to the supply voltage or provide resistance against the gate’s driver when the output is supposed to be low.

Local Wire

A wire that connects transistors to form a gate or connects closely located gates to create a subsystem. The length of local wires is expected to decrease with technology scaling, and their delay performance does not significantly improve with scaling.

LOCOS (Local Oxidation of Silicon)

A traditional CMOS fabrication technique where areas containing transistors are covered with thin oxide, while the areas between transistors are covered with thick field oxide to provide isolation.

Logic Block (Cell)

The smallest reconfigurable unit in an FPGA (Field-Programmable Gate Array). It typically contains components like Lookup Tables (LUTs), D Flip-Flops (DFFs), and multiplexers. Logic cell design aims to allow versatile reconfiguration without wasted hardware.

Logic Family

A method of designing logic gates with shared architectural features, area, power characteristics, delay, and Voltage Transfer Characteristic (VTC) behavior. Gates from the same logic family are assumed to work together in designs.

Logic Threshold

The point on a gate’s Voltage Transfer Characteristic (VTC) where input and output voltages are equal. Inputs above the threshold produce lower outputs, while inputs below it produce higher outputs. This threshold point is a stable but often metastable reference.

Logical Effort

A dimensionless value represents how much harder it is for a gate to drive a copy of itself compared to an inverter driving a copy of itself. Inverters have a logical effort of 1. It helps find optimal gate sizing in logic gate chains.

Logical Hazard

A transient glitch in the output of a combinational logic circuit caused by differential delays in multiple paths for the same signal. If not registered, glitches must be removed to prevent incorrect results in successive gates.

Low-Impedance Node

A node in an electronic circuit that has a low-impedance path to either the power supply (VDD) or ground (GND). In static CMOS gates, the output node must be a low-impedance node for all possible input combinations as per the truth table.

LUT (Look-Up Table)

A simple and compact memory unit, often implemented as a register file. LUTs are notably used for realizing complex functions, including transcendental functions, and as fundamental building blocks in Field-Programmable Gate Arrays (FPGAs).


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