Digital CMOS Abbreviation QR Alphabet Dictionary

Digital CMOS

Quantization Error

Quantization error refers to the error introduced when representing a real-numbered value as a fixed-point number with a limited number of bits. It is the difference between the actual value and the quantized value, leading to rounding or truncation errors in digital arithmetic.

Quantization Signal-to-Noise Ratio (QSNR)

QSNR is a metric primarily associated with fixed-point operations. It quantifies the ratio of the power in the truncated (quantized) output of an operation to the power of the quantization error or noise. QSNR is used to determine if the register size in a fixed-point design is sufficiently large to minimize quantization errors.

Quasi-Fermi Level

Quasi-Fermi levels are virtual energy levels used in materials that are not in thermal equilibrium. In such materials, where the mass action law does not hold, quasi-Fermi levels are introduced to describe carrier concentrations. There are separate quasi-Fermi levels for electrons and holes. In thermal equilibrium, these levels collapse onto the real Fermi level.

Random Defects

Random defects are defects or imperfections in semiconductor wafers that are distributed randomly across the wafer’s surface. They can occur for various reasons and tend to have a fairly uniform distribution. Unlike systematic defects, which follow specific patterns, random defects are more unpredictable and can impact yield in semiconductor manufacturing.

Read Pointer (FIFO)

In a First-In-First-Out (FIFO) buffer, the read pointer indicates the next position from which data will be read. The receiver controls the read pointer, and its updates are synchronized with the receiver’s clock. To calculate the full flag, the read pointer often undergoes Gray encoding, which ensures that only one bit changes at a time during updates.

Recovery Time

Recovery time, in the context of latches, is analogous to setup time. It is the time required for a latch to return to a stable state after the input changes. This property is essential to ensure correct latch operation.

Rectifying Contact

A rectifying contact refers to a metal-semiconductor contact that allows conduction in only one direction. In the other direction, there exists a significant energy barrier that restricts the flow of majority carriers, permitting only residual current. Rectifying contacts are sometimes used to create Schottky diodes, but in most cases, they are considered undesirable and are failed ohmic contacts.

Refresh (DRAM)

In Dynamic Random-Access Memory (DRAM), refresh is the process of reading, amplifying, and then rewriting all the bits stored in the memory cells. This is done row by row in a cyclical manner. Refreshing is necessary because leakage leads to a gradual loss of charge from the storage capacitors in DRAM cells.

Regenerative Property

The regenerative property is a characteristic of certain logic families where electrical values in the transition region of the Voltage Transfer Characteristic (VTC) are restored to one of the stable regions after passing through multiple logic stages. Regenerative logic families must have an absolute gain in the transition region to ensure proper operation.


A register is a type of sequential circuit in which the enable signal is edge-triggered. During a specific edge (usually rising or falling) of the clock signal, the register becomes transparent, allowing the input to pass through to the output. Registers are commonly used as storage elements in synchronous digital circuits.

Register Propagation Delay

For a register, the register propagation delay is the time interval after the active clock edge when the output changes in response to a change in the input. This delay is sometimes referred to as a “clock-to-Q” delay because it occurs entirely within the circuitry of the slave latch.


Reliability refers to the ability of a circuit or system to function correctly and consistently over an extended period of use. It is often quantified in terms of failure rate and mean time between failures (MTBF). Reliability is crucial in critical systems where failures can have serious consequences.

Removal Time

Removal time, in the context of latches, is analogous to hold time. It is the time interval during which the input must remain stable after the clock edge to ensure proper latch operation.

Resistive Load Logic

Resistive load logic is a type of ratioed logic family in which the driver is typically a MOSFET (or occasionally a BJT), and the load is a passive resistor. In this logic family, a logic high output value corresponds to the full supply voltage, but achieving a sufficiently low logic low output voltage requires a relatively large resistor. This logic family tends to have high static power dissipation.

Reverse-Biased PN Junction

A reverse-biased PN junction occurs when an external voltage is applied with a positive polarity to the N-type side of the junction. This widens the depletion region, strengthens the built-in electric field, and saturates minority carrier extraction from either side of the junction. It results in very low current flow in the reverse direction.

Ripple Carry Adder

A ripple carry adder is the simplest form of an N-bit adder. It consists of full adders connected in series, where the carry-out of one full adder becomes the carry-in of the next. However, this causes delays as each bit must wait for the previous bits to complete their calculations, resulting in a linear increase in delay with the number of bits.

Rise Time

Rise time is the time it takes for a signal to transition from a logic low (0) to a logic high (1). It specifically measures the rising slope of the waveform.


Routing is the process of connecting standard cells in an Application-Specific Integrated Circuit (ASIC) or logic cells in a Field-Programmable Gate Array (FPGA). It is a critical step in the design process where interconnections are established to enable data flow and communication between components.

Routing Channel (ASIC)

In ASIC design, a routing channel refers to a horizontal channel containing metal lines that run between rows of standard cells. These channels facilitate long-range horizontal communication between cells, while vertical connections are typically made in higher metal layers.

Routing Channel (FPGA)

In FPGA design, a routing channel is a programmable channel that runs between logic cells or islands of logic cells. These channels are used for programmable connections using switches in a switch fabric where routing channels intersect.

Row Decoder

A row decoder is a true decoder used to select the word lines of a memory bank in a memory array. It decodes a portion of the address bus to enable a specific row for read or write operations.

Row Decoder Replica

A row decoder replica is essentially a dummy circuit designed to replicate the delay characteristics of the actual row decoder. It doesn’t have to be constructed the same way as the row decoder but should mimic its delay behavior. Row decoder replicas are used in self-timed memory designs to introduce a delay in the sense amplifier enable signal.

RTL (Register Transfer Language)

RTL, which stands for Register Transfer Language, is an alternative term used for Hardware Description Languages (HDLs). A significant part of HDLs involves specifying how data is transferred between registers in consecutive clock cycles.


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