Maskable Interrupt
An interrupt that can be disabled or ignored by the CPU instructions is called a Maskable Interrupt. These interrupts can be either edge-triggered or level-triggered.
Non-Maskable Interrupt
A Non-Maskable Interrupt (NMI) is an interrupt that cannot be disabled or ignored by the CPU instructions. It is often used when response time is critical or when an interrupt should never be disabled during normal system operation.
Difference between Maskable and Non-Maskable Interrupt
| SR.NO. | Maskable Interrupt | Non-Maskable Interrupt |
|---|---|---|
| 1 | Maskable interrupt can be disabled or ignored by the CPU. | A non-maskable interrupt cannot be disabled or ignored by the CPU. |
| 2 | When a maskable interrupt occurs, it can be handled after executing the current instruction. | When non-maskable interrupts occur, the current instructions and status are stored in the stack for the CPU to handle the interrupt. |
| 3 | Maskable interrupts help to handle lower-priority tasks. | Non-maskable interrupts help to handle higher priority tasks such as a watchdog timer. |
| 4 | Used to interface with peripheral devices. | Used for emergency purposes (e.g., power failure, smoke detector, etc.). |
| 5 | In maskable interrupts, response time is high. | In non-maskable interrupts, response time is low. |
| 6 | It may be vectored or non-vectored. | All are vectored interrupts. |
| 7 | The operation can be masked or made pending. | The operation cannot be masked or made pending. |
| 8 | Examples include RST6.5, RST7.5, and RST5.5 of 8085. | An example is the Trap of the 8085 microprocessor. |
