Physical Design Engineer Interview Questions & Answers
DIBL GIDL BTBT and Tunneling Effect in CMOS Devices |
What are the advantages of generating clocks internally? |
List of Sanity Checks in Physical Design |
Module Constraint Types: Guide, Fence, and Region |
What are the inputs of LVS? |
What is insertion delay? |
Significance of Generated Clock and Virtual Clock |
Why double via insertion? |
What is the impact of IR drop in cell delay? |
Antenna Effect in VLSI – Causes and Solution. |
What is metal slotting? |
Sources of on-chip variation (OCV) |
Temperature Inversion on Lower Nodes |
How does the virtual clock help in the physical design process? |
What is CMP (chemical mechanical polishing)? |
What is the dishing effect? |
What is the content in the .lib, .lef & .tlef files |
What is metal fill insertion? |
What is input and output delay? |
What are the OCV & AOCV? |
How to fix setup and hold violations at a time? |
What is cross-talk? |
What are DRC & how will you fix them? |
How to fix setup and hold violations? |
What is the use of placement blockage? |
Can virtual clock analysis accurately predict the timing of the physical implementation? |
What are clock gating and power gating? |
Reasons for Metastability in VLSI |
How can you reduce dynamic power? |
What are the types of physical verification? |
Why is the generated clock necessary in physical design? |
What is temperature inversion? |
What are metal ECO and Base ECO? |
Process Variation in VLSI |
Process Corners in VLSI |
Types of violations in LVS? |
How to fix Electromigration (EM)? |
What is the Clock Period and Levels of the Clock |
Interview questions for experienced Physical Design Engineer |
What are Physical design inputs in detail? |
What is Electro migration and how to reduce it? |
Difference Between Clock Skew and Uncertainty |
What is the difference between ASIC and FPGA? |
How to fix Dynamic IR drop? |
Which parameters decide the Spacing between Macros |
What is Dynamic Power? |
What are the inputs of LVS? |
What are the inputs for synthesis? |
How to decide channel width between macros? |
What information is presented in DEF? |
What is the flow of your project? |
How to fix setup violations? |
What is HVT, LVT, and ULVT cells? |
What is the difference between crosstalk delay and crosstalk noise? |
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RTL & Verilog Design Forum |
Semiconductor Forum |
Analog Layout Design Interview Questions | Memory Design Interview Questions |
STA Interview Questions | Verilog Interview Questions |
Digital Design Interview Questions |
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