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Digital Electronics Interview Question

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Digital Electronics Interview Question With Answers.

Digital Electronics Interview Question

 

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SRAM full form
DRAM Full Form
VLSI Full Form
CMOS Inverter
Tunnel Diode
What are VIAs in VLSI?
Metal-Semiconductor Contact
Optical Proximity Correction (OPC) in VLSI
Metal Semiconductor ohmic Contact
The Number of Metal Layers in Layout Design
I have two cases: ( Case1: One metal has 2um width and 10um length, case2: Two metals are running partially with 1um width and 10um length for each of two) So from a layout perspective, which case is best and why?
Difference between CPLD and FPGA
State the De Morgan’s Theorem
Damascene Technique in VLSI
Binary numbers
Decimal numbers
AND Gate: Symbol, Truth Table, Working, Circuit Diagram
NOR Gate- Symbol, Truth Table, and Circuit Diagram
OR Gate-Symbol, Truth Table, and Circuit Diagram
NAND Gate- Symbol, Truth Table, Circuit Diagram
What Is Noise Margin in VLSI
Cascaded CMOS Inverters
Are there any limitations to using cascaded CMOS inverters?
Thermal Oxidation: Understanding the Formation and Processes
Are cascaded CMOS inverters more prone to signal delays?
Why do we gradually increase the size of a CMOS inverter in each cascaded stage?
How do You adjust the CMOS inverter to either reduce leakage or decrease delay?
What happens when resistance is placed in the place of PMOS in a CMOS inverter circuit?
Why NAND Gate is Better than NOR Gate?
Metallization Layers in Semiconductor Chips: Aluminum vs. Copper
Wet Etching vs. Dry Etching: A Comparative Analysis
Regions of the MOSFET
Differences between LDD(lightly doped drain) & Halo Doping
Why do we need a capacitor in DRAM?
What’s the difference between Design Rule Check (DRC) and Design for Manufacturability (DFM)?
Which type of current is flowing in the CMOS Inverter?
Design3:8 Decoder Using 2:4 Decoders
Johnson Ring Counter
Ring Counter in Digital Logic
Difference between Ring Counter and Johnson Counter
Ripple Counter in Digital Logic
Bi-Directional Counter
N Type Semiconductor
P Type Semiconductor
Intrinsic Semiconductor
Extrinsic Semiconductor
Difference Between p-Type and n-Type Semiconductor
Difference Between Intrinsic and Extrinsic Semiconductor
Difference between Straight and Twisted Ring Counter
Types of Sequential Circuits
Clock Signal and Triggering
Toggle or T flip-flop
2:1 MUX Using NAND
Master-Slave D Flip-Flop
D Flip Flop Using MUX
D Latch Using MUX
Design 4:1 Mux Using 2:1 Mux
Logic Gates
What is Substrate coupling in VLSI?
What is Different Logic family
Importance of Clock Distribution Network in VLSI
Why PMOS and NMOS are sized equally in Transmission Gates?
Which transistor has higher gain, BJT or MOS and why?
Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
Why not give the output of a circuit to one large inverter?
Why do we gradually increase the size of inverters in buffer design?
Can cascaded CMOS inverters be used in low-power applications?
Can be cascaded CMOS inverters improve noise immunity in digital circuits?
Why cascaded CMOS inverters of different ratios are better than a single inverter?
What is Charge Sharing in CMOS
CMOS logic, give the various techniques you know to minimize Power Consumption.
How does the Resistance of the metal lines vary with increasing thickness and increasing length?
What are the limitations in increasing the power supply to reduce delay?
What happens to delay if we include a resistance at the output of a CMOS circuit?
What happens to delay if you increase load capacitance?
Explain the sizing of the inverter in CMOS
Enhancement Mode of MOSFET
Depletion Mode of MOSFET
Inversion Mode of MOSFET
Different Types of IC Packaging
What is a GDS file
What is the role of ERC in VLSI?
What are the steps involved in semiconductor device fabrication?
What is the feedback in VLSI?
Temperature Inversion on Lower Nodes

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