Digital Electronics Interview Question(2025)

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2:1 MUX Using NAND
AND Gate: Symbol, Truth Table, Working, Circuit Diagram
Are cascaded CMOS inverters more prone to signal delays?
Are there any limitations to using cascaded CMOS inverters?
Bi-Directional Counter
Binary numbers
Can be cascaded CMOS inverters improve noise immunity in digital circuits?
Can cascaded CMOS inverters be used in low-power applications?
Cascaded CMOS Inverters
Clock Signal and Triggering
CMOS Inverter
CMOS logic, give the various techniques you know to minimize Power Consumption.
D Flip Flop Using MUX
D Latch Using MUX
Damascene Technique in VLSI
Decimal numbers
Depletion Mode of MOSFET
Design 4:1 Mux Using 2:1 Mux
Design3:8 Decoder Using 2:4 Decoders
Difference between CPLD and FPGA
Difference Between Intrinsic and Extrinsic Semiconductor
Difference Between p-Type and n-Type Semiconductor
Difference between Ring Counter and Johnson Counter
Difference between Straight and Twisted Ring Counter
Differences between LDD(lightly doped drain) & Halo Doping
Different Types of IC Packaging
DRAM Full Form
Enhancement Mode of MOSFET
Explain the sizing of the inverter in CMOS
Extrinsic Semiconductor
How do I get Vias resistance information within a new process?
How do You adjust the CMOS inverter to either reduce leakage or decrease delay?
How does the Resistance of the metal lines vary with increasing thickness and increasing length?
How to succeed as a digital designer.
I have two cases: ( Case1: One metal has 2um width and 10um length, case2: Two metals are running partially with 1um width and 10um length for each of two) So from a layout perspective, which case is best and why?
Importance of Clock Distribution Network in VLSI
Intrinsic Semiconductor
Inversion Mode of MOSFET
Johnson Ring Counter
Logic Gates
Master-Slave D Flip-Flop
Metal Semiconductor ohmic Contact
Metallization Layers in Semiconductor Chips: Aluminum vs. Copper
Metal-Semiconductor Contact
N Type Semiconductor
NAND Gate- Symbol, Truth Table, Circuit Diagram
NOR Gate- Symbol, Truth Table, and Circuit Diagram
Optical Proximity Correction (OPC) in VLSI
OR Gate-Symbol, Truth Table, and Circuit Diagram
P Type Semiconductor
Regions of the MOSFET
Ring Counter in Digital Logic
Ripple Counter in Digital Logic
SRAM full form
State the De Morgan’s Theorem
Temperature Inversion on Lower Nodes
The Number of Metal Layers in Layout Design
Thermal Oxidation: Understanding the Formation and Processes
Toggle or T flip-flop
Tunnel Diode
Types of Sequential Circuits
VLSI Full Form
Wet Etching vs. Dry Etching: A Comparative Analysis
What are the limitations in increasing the power supply to reduce delay?
What are the steps involved in semiconductor device fabrication?
What are VIAs in VLSI?
What happens to delay if we include a resistance at the output of a CMOS circuit?
What happens to delay if you increase load capacitance?
What happens when resistance is placed in the place of PMOS in a CMOS inverter circuit?
What is a GDS file
What is Charge Sharing in CMOS
What is Different Logic family
What Is Noise Margin in VLSI
What is Substrate coupling in VLSI?
What is the feedback in VLSI?
What is the role of ERC in VLSI?
What is the use of CMOS in VLSI?
What’s the difference between Design Rule Check (DRC) and Design for Manufacturability (DFM)?
Which transistor has higher gain, BJT or MOS and why?
Which type of current is flowing in the CMOS Inverter?
Why cascaded CMOS inverters of different ratios are better than a single inverter?
Why do we gradually increase the size of a CMOS inverter in each cascaded stage?
Why do we gradually increase the size of inverters in buffer design?
Why do we need a capacitor in DRAM?
Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
Why NAND Gate is Better than NOR Gate?
Why not give the output of a circuit to one large inverter?
Why PMOS and NMOS are sized equally in Transmission Gates?