What is the purpose of timing analysis?
The primary objective of static timing analysis (STA) is to ensure that despite potential variations, all signals will arrive neither too early nor too late, thereby guaranteeing proper circuit operation. STA’s capability to verify every path allows it to detect additional issues such as glitches, slow paths, and clock skew..
List the ideal conditions for the timing path.
The basic static timing equations:
Clock period > T cq + T pd + T su
Tcq is the maximum time from clock to output; Tpd is the maximum propagation delay time through the logic and Tsu is the maximum setup time.
For Hold time
Hold time < Tmin (R) + Tmin (logic)
Where Tmin (R) and Tmin (logic) are the minimum delays by register and logic respectively.
For Clock period
Clock period + clock skew > T cq + T pd + Tmin (logic)
Where clock skew is a spatial delay of the clock. For the clock period,
Hold time + clock skew < T cq + T pd + Tmin (logic)
Clock period − jitter (worst case) > T cq + T pd + T su
Hold time + jitter (worst case) < Tmin(R) + Tmin(logic)
The situation where the rising edge is late and the falling edge is early is the worst case of jitter.
Worst case jitter = 2 × jitter
Therefore, the maximum Tcq, Tpd, and Tsu rely on the maximum operating frequency of operation (1/clock period). By adjusting the temperature and clock frequency, the setup violation can be resolved. The device becomes faster when the temperature lowers the threshold voltage even further. It is not possible to correct the hold time violation by altering the clock frequency.
How will you calculate negative and maximum borrow time?
#The discrepancy between the data arrival time and the clock edge can be used to determine the negative time borrow.
Negative borrow time = Arrival time-clock edge
The negative borrow time states that there is no borrowing takes place.
Maximum borrow time = clock pulse width-library setup time
To arrive at the maximum borrow time, clock latency and the library time at the end of the latch are both deducted from the clock pulse width.
What do you mean by positive, negative, and zero slack?
#The slack is what determines the frequency or speed of the particular design. It can be calculated as follows and is connected to the timing path
Slack = Actual time-desired time
Negative slack
This means, there is some timing violation. The design has not achieved a specific speed or frequency.
positive slack
This means the design is achieving a specific speed or frequency and It has some extra margin as well.
Zero slack
This slack signifies that there is no margin, but the designer is already working on the exact speed or frequency.
