Net Delay

Net delay is the difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net. It is also known as a wire delay. This is the output pin of the cell to the input pin of the next cell.

List the parameters on which net delay or cell delay depends.

The net delay or cell delay depends on the following parameters  #

• Input skew
• External delay
• Wire load model
• Library setup time
• Library delay model
• Operating conditions
• Back annotated delay
• Cell load characteristics
• Cell drive characteristics

Input skew and output skew

All input signals within a clocking block will be sampled at skew time units before the clock event if an input skew is mentioned for that block. All output signals in a clocking block will be driven skew time units after the appropriate clock event if an output skew is mentioned for that block. #

Output delay is the time required by the external circuit before which the data has to arrive at the output pin of the block with respect to the reference clock.

What are the different types of delays in ASIC or VLSI design?

Different Types of Delays in ASIC or VLSI design are the following #

1. Propagation Delay
2. Phase Delay
3. Transition Delay
4. Path Delay
5. Net delay,
6. Cell Delay
7. Intrinsic Delay
8. Extrinsic Delay
9. Input Delay
10. Output Delay
11. Exit Delay
12. Network Delay
13. Insertion Delay

List the types of delay models used to estimate the delay.

• RLC model    #
• Wire load model
• Lumped RC model
• Elmore delay model
• Distributed RC model
• Transmission line model
• Lumped capacitor model