Close Menu
  • Analog Design
    • Latest Analog Layout Interview Questions (2025)
  • Digital Design
    • Digital Electronics Interview Question(2025)
    • Top VLSI Interview Questions
  • Physical Design
    • Physical Design Interview Questions for VLSI Engineers
  • Verilog
    • Verilog Interview Questions(2024)
  • Forum
Facebook Instagram YouTube LinkedIn WhatsApp
SiliconvlsiSiliconvlsi
Forum Questions Register in Forum Login in Forum
Facebook Instagram YouTube LinkedIn WhatsApp
  • Analog Design
    • Latest Analog Layout Interview Questions (2025)
  • Digital Design
    • Digital Electronics Interview Question(2025)
    • Top VLSI Interview Questions
  • Physical Design
    • Physical Design Interview Questions for VLSI Engineers
  • Verilog
    • Verilog Interview Questions(2024)
  • Forum
SiliconvlsiSiliconvlsi
Home»Physical Design»Time Borrowing Concept
Physical Design

Time Borrowing Concept

siliconvlsiBy siliconvlsiOctober 5, 2022Updated:January 11, 2025No Comments2 Mins Read
Facebook Pinterest LinkedIn Email WhatsApp
Share
Facebook Twitter LinkedIn Pinterest Email
Time Borrowing Concept
Time Borrowing Concept

What is Time Borrowing Concept?

A shorter path can borrow time from the following path of later logic using the simple term-time borrowing technique. Since time borrowing slows down data arrival time and increases data arrival time, it often has an impact on setup.

What are the main characteristics of the time-borrowing concept?

  • Time borrowing can be multistage.
  • It should be held in the same clock cycle.
  • Time borrowing affects setup slack calculation.
  • Time borrowing slowdowns the data arrival time.
  • Hold slack calculation is not affected by time borrowing because the fastest data is used by hold time
  • In time borrowing, the same phase of the same clock should be used to accomplish both data launching and capturing. Time borrowing will stop working if the launching and capturing are not in sync.

What is the difference between time-borrowing and time-stealing?

  • Time borrowing is a technique used to transfer time from the smaller paths of the following design stages to the longer path. Time stealing is the process of changing the clock cycle for Flip-flop 2 in accordance with the time of data arrival.
  • Latch-based designs use time borrowing, whereas flip-flop-based designs use time stealing.
  • The clock phase is not disturbed in the time-borrowing notion. Through the pipeline, the latch automatically uses the slack from the previous cycle. In contrast, time theft reduces the amount of time available for the subsequent stage. The designer will take care that the phase shift and clock period differences between the next stage delay and the current stage delay are less than one.

 

Share. Facebook Twitter Pinterest LinkedIn Tumblr Email

Related Posts

Why Are Metals Good Conductors of Electricity?

November 21, 2024

Difference between Mesh Topology and Tree Topology

March 24, 2024

What’s the difference between Design Rule Check (DRC) and Design for Manufacturability (DFM)?

October 26, 2023
Leave A Reply Cancel Reply

Facebook X (Twitter) Instagram Pinterest Vimeo YouTube
  • About Us
  • Contact Us
  • Privacy Policy
© 2025 Siliconvlsi.

Type above and press Enter to search. Press Esc to cancel.