In CMOS (Complementary Metal-Oxide-Semiconductor), charge sharing occurs when charge unintentionally transfers between different nodes or capacitors in a circuit, affecting its intended operation. It happens when nodes with different voltage potentials are temporarily connected during certain circuit actions.
Charge sharing is more prevalent in dynamic circuits like dynamic logic gates or dynamic memory cells, where nodes are dynamically charged and discharged. During switching, the voltage on a stable node may temporarily change due to charge redistribution with neighboring nodes.
This phenomenon is caused by parasitic capacitances between circuit elements like gate capacitances, interconnect capacitances, and diffusion capacitances. When a high-voltage node connects to a low-voltage node, the charge redistributes, decreasing the voltage on the high-voltage node and increasing the voltage on the low-voltage node. This unintentional charge redistribution can lead to logic errors or disturb stored data in memory cells.
Charge sharing is problematic as it introduces delay, increases power dissipation, and affects circuit reliability and accuracy. Designers use techniques to mitigate charge sharing, such as optimizing circuit layouts, sizing and shielding transistors, implementing voltage boosting methods, or employing charge-sharing immune circuit topologies.