Worst and Best Timing Path The path which is having the largest delay is known as the worst path, late…
Author: siliconvlsi
What is Time Borrowing Concept? A shorter path can borrow time from the following path of later logic using the…
Critical path, false path, and multicycle path Critical path The critical path is considered that timing-sensitive to the functional path…
What are the main reasons for setup or hold time violations? Main reasons for setup or hold time violations Design…
What do you mean by Launch and capture edge? #The launch edge is the active edge of the clock at…
Static random-access memory In SRAM memory, a single cell stores 1 bit of data. This data bit is represented by…
Why PMOS pass strong 1 and weak 0 The current equation for PMOS is the following, for PMOS to turn…
Why NMOS pass strong 0 and weak 1 We all know that when Vgs > Vt, at that time only…
Which input files are required to run STA • Parasitic files • Gate-level netlist • Constraints • General setup scripts.…
Negative bias temperature instability When we applied a Negative voltage to the gate, dangling bonds called traps developed between the…