Worst and Best Timing Path
- The path which is having the largest delay is known as the worst path, late path, or maximum path, i.e. using this path, the data takes the maximum time to reach the endpoint.
- The path that has the minimum delay is known as an early path, the best path, or the minimum path.
What do you understand by time stealing?
#The idea of time stealing is to change the clock phase at flip-flop 2 so that the timing constraints are not violated by the data arrival time at the capture edge of flip-flop 2. When a certain logic partition requires more time and was supposed to be deterministic at startup, time theft is used.
|Analog and Memory Layout Design Forum
|Physical Layout Design Forum
|RTL & Verilog Design Forum
|Analog Layout Design Interview Questions
|Memory Design Interview Questions
|Physical Design Interview Questions
|Verilog Interview Questions
|Digital Design Interview Questions
|STA Interview Questions