What is Circuit Extraction?
Circuit Extraction involves determining various parameters of a layout under design, including transistor dimensions, parasitic capacitance/resistance, and the connectivity of the components. The extraction of parasitic capacitance/resistance becomes particularly challenging in designs with deep sub-micron features.
In the context of circuit extraction tools, two main approaches are discussed:
Flatten Extraction
Some circuit extraction tools flatten the entire circuit, meaning they remove the hierarchy present in the layout before conducting the extraction.
This method simplifies the extraction process but may result in a loss of information regarding the original hierarchy.
Hierarchical Extraction
More advanced circuit extraction tools perform extraction hierarchically, preserving the original hierarchy of the layout.
A hierarchically extracted circuit provides a more efficient model for subsequent operations, such as simulation.
The extracted netlist can also be compared against a schematic using Layout versus Schematic (LVS) tools for verification purposes.