Clock Period (ns)
Data Path Delay (ns)
Setup Time (ns)
Launch Clock Arrival (ns)
Capture Clock Arrival (ns)
Existing Clock Jitter (ns)
Clock skew is the difference in clock arrival time between the launch and capture flip-flops. It occurs because the clock signal may travel through different clock tree paths and reach different sequential elements at different times.
Clock jitter is the variation of a clock edge from its ideal timing position. Jitter reduces the timing margin available for data transfer and must therefore be considered during static timing analysis.
- Positive Clock Skew: Capture clock arrives later than the launch clock and can improve setup timing.
- Negative Clock Skew: Capture clock arrives earlier than the launch clock and can reduce setup timing margin.
- Clock Jitter: Variation in clock edge timing that reduces the available timing budget.
Clock Skew = Capture Clock Arrival − Launch Clock Arrival
Remaining Jitter Budget = Clock Period − Data Path Delay − Setup Time − Clock Skew − Existing Jitter
Where:
- Clock Period (Tclk): Time between two consecutive active clock edges.
- Data Path Delay (Tdata): Delay from the launch flip-flop through the combinational logic to the capture flip-flop.
- Setup Time (Tsetup): Minimum time for which data must be stable before the capture clock edge.
- Launch Clock Arrival: Time at which the clock edge reaches the launch flip-flop.
- Capture Clock Arrival: Time at which the clock edge reaches the capture flip-flop.
- Existing Clock Jitter: Known clock timing variation already included in the timing budget.
A positive remaining jitter budget indicates that additional clock jitter can be tolerated within the simplified timing budget. A zero or negative value indicates that the available timing margin has been exhausted.