Difference between statistical and conventional STA
Statistical static timing analysis (SSTA) and conventional static timing analysis (STA) are both techniques used to verify the timing performance of digital circuits, but they differ in how they approach the problem.
Traditional STA is a deterministic method that determines the timing of a circuit using a set of timing constraints, such as maximum and minimum delays. This method makes the assumption that all circuit delays are constant and known and that all circuit inputs are known at the time of analysis.
Statistical STA considers the variability of delays brought on by manufacturing procedures, temperature, voltage, and aging effects. The major objective is to determine the likelihood of timing violations while accounting for the ambiguity of the circuit delays. This method uses Monte Carlo simulations to carry out numerous timing analysis runs with various delay values in order to acquire a distribution of the timing results. Statistical models are used to describe the variability of the delays.
It is different from conventional deterministic traditional STA in the following ways:
- The run time is linear.
- It can be used for circuit optimization.
- In statistical STA, there is no chance of missing paths, as it does not have any vectors.
- It cannot handle spatial correlation within the die, which is possible in the case of deterministic STA.
- There are correlational problems while using statistical STA, it needs more corners to resolve design issues.
