Domino CMOS Logic
Domino CMOS logic represents a modified version of dynamic CMOS logic circuits. It addresses the issue of cascading dynamic CMOS logic circuits by introducing static inverters at the outputs of these dynamic blocks. Figure 1 illustrates a cascaded domino CMOS logic circuit.
How It works
- Pre-Charge Phase (φ = 0): During this phase, the outputs of the dynamic CMOS logic circuits are pre-charged to a logic high state (1), and the output of the static inverter is at logic low (0).
- Evaluation Phase (φ = 1): In this phase, the outputs of the dynamic CMOS logic circuits can either transition to logic low (0) or remain at logic high (1). Importantly, the output of the static inverter can only make a transition from 0 to 1 during this phase. This means that regardless of the input logic conditions, the static inverter’s output cannot transition from 1 to 0 during the evaluation phase.
Advantage of Domino CMOS
One significant advantage of Domino CMOS is its ability to reduce the number of transistors required compared to static CMOS logic. In static CMOS logic, 2N transistors are needed to implement an N-input logic function. In dynamic CMOS logic, you require only N + 2 transistors, and Domino CMOS logic adds just two more transistors. Additionally, it effectively handles the cascading problem encountered in dynamic CMOS logic.
However, it’s important to note that Domino CMOS logic is most suitable for non-inverting logic functions, meaning logic expressions without complements over the entire expression. For inverting logic, where complements are involved, the expression needs to be reorganized to eliminate the complements before it can be efficiently implemented using Domino CMOS logic.
