Why is using dummy poly in some standard cell rows considered harmful in FinFET nodes?

Dummy poly in just some standard cell rows can cause trouble because it makes the environment uneven. In FinFET nodes, even small differences like that can lead to mismatch in transistor behavior. We try to keep things uniform across rows so all devices see the same conditions.

From what we've seen, the problem is that dummy poly affects stress and parasitics. If you only add it in certain rows, you change the local strain and it can shift transistor performance. We always aim for consistent dummy usage across the full chip, not just in parts. That way, you don’t run into surprises during silicon testing.