Fault Model in VLSI
To measure how good a test is, we use something called “fault coverage.” It’s a ratio. On the top is the number of faults the test finds, and on the bottom is the total possible number of faults. We figure this out by running a test experiment where we pretend there are faults and see if the test catches them. If the circuit reacts differently than it should, we know we’ve found a fault.
Now, to make these tests, we need some models of the kinds of faults that can happen. These models represent different types of problems that can occur in the chip. There are a bunch of these models, but we’ll look at a few:
Stuck-at-Fault Model
This one pretends that a wire is always stuck at either 0 or 1. Imagine a light switch that’s always on or always off.
Stuck-Open Fault Model
Here, it’s like a transistor is permanently turned off, which makes the chip act differently. This is unique to certain types of circuits.
Bridging Fault Model
This one imagines that two wires are accidentally connected, which can change how the chip works.
Transition Delay Fault Model
It’s similar to the stuck-at model, but instead of always being 0 or 1, it looks at how long it takes for a signal to change from 0 to 1 or from 1 to 0.
Path Delay Fault Model
This considers how long it takes for a signal to travel along a whole path in the circuit.
Current-Based Fault Model
Some faults don’t cause logic errors but create problems with how much electric current flows. This is important, especially when the chip isn’t doing anything.
Finally, when we make these tests, we usually assume there’s only one fault at a time. This simplifies things a lot. So, we create tests for one fault, then another, and so on. This helps us catch lots of different issues and ensures the chip works well.