In modern CMOS technology, polysilicon is favored as the gate electrode material because it can withstand the high temperatures required for activating the source/drain implants. This entire process ensures the proper formation of source/drain extensions for NMOS and PMOS devices in integrated circuits.
Formation of Source/Drain Extensions
- NMOS Source/Drain Extension Formation: This process begins by using photolithography. A layer of resistance is applied and patterned to expose the NMOS (n-channel) devices.
- Implantation: A low-energy phosphorus implant is performed. This implantation process creates the n-channel, low-doped drain (nLDD) extensions. Importantly, the presence of the polysilicon gate ensures that this implantation aligns precisely with the gate structure.
- Preventing Punchthrough: A deep boron pocket implant is often used at this stage to prevent source/drain punchthrough in the NMOS devices. This implant helps maintain the integrity of the device.
- Resist Removal: After these processes, the photoresist layer is removed, resulting in a structure that shows the NMOS source/drain extensions.
P-Channel Source/Drain Extension Formation
- Photolithography for PMOS: In a similar fashion, a new photolithography step (mask layer 6) is performed to protect NMOS devices with resist, exposing the PMOS (p-channel) devices.
- Implantation for PMOS: Boron is implanted at low energy to create the p-channel low-doped drain (pLDD) extensions. The polysilicon gate ensures precise alignment of this implantation.
- Suppressing Punchthrough for PMOS: Much like the NMOS, a deep phosphorus pocket implant may be used to suppress punchthrough in the PMOS devices.
- Resist Removal for PMOS: After completing these processes, the photoresist layer is removed, resulting in the structure displaying the PMOS source/drain extensions.
Formation of Gate Sidewall Spacers
- Deposition of Nitride: To prepare for the actual source/drain implants, a conformal layer of silicon nitride (or sometimes CVD oxide) is deposited using LPCVD.
- Etching Nitride for Spacer Formation: After depositing nitride, it is etched to form the gate sidewall spacers. These spacers serve as both a mask for the source/drain implants and a barrier for subsequent processes, such as salicide formation. The etching process is anisotropic, meaning it primarily removes material in one direction, forming the spacers.
- NMOS Source/Drain Formation: During the source/drain implants, the combination of the polysilicon gate and spacers blocks the implantation process. This self-alignment ensures that the implants align precisely with the gate and LDD extensions. Photolithography (mask layer 5, second use) is used to protect the PMOS devices with resist, exposing the NMOS devices.
- Implantation for NMOS: A relatively low-energy, high-dose arsenic implant is performed to create the n+ regions. This implant also forms the necessary n+ ohmic contacts.
- Resist Removal for NMOS: After the implantation, the resist layer is stripped, resulting in the structure displaying the NMOS source/drains.
- PMOS Source/Drain Formation: The same process is repeated for PMOS source/drains. Photolithography (mask layer 6, second use) and a low-energy, high-dose BF2 implant are used.
- Resist Removal for PMOS: After completing the implantation, the resist layer is removed, resulting in the structure displaying the PMOS source/drains .
What is Annealing?
The source/drain module concludes with a high-temperature annealing process. This anneal step serves to electrically activate the implants and re-crystallize any damaged silicon in the devices.
Use of Polysilicon Gate
In modern CMOS technology, one reason for choosing polysilicon as the gate electrode material is its ability to withstand the high temperatures required for activating the source/drain implants.
What is the purpose of the low-energy phosphorus implant in the source/drain module, and which type of transistors (NMOS or PMOS) does it primarily impact?
The low-energy phosphorus implant is used to form the n-channel, low-doped drain (nLDD) extensions. These extensions are primarily associated with NMOS (n-channel) transistors. They serve to suppress hot carrier injection into the gate and reduce short-channel effects.
How does the presence of the polysilicon gate contribute to the self-alignment of the source/drain extensions in the semiconductor manufacturing process?
The presence of the polysilicon gate inherently leads to the self-alignment of the source/drain extensions with respect to the gate electrodes. This self-alignment simplifies the manufacturing process and ensures precise placement of the extensions.
What is the purpose of the deep boron pocket implant, and in which type of transistors (NMOS or PMOS) is it commonly used?
Answer: The deep boron pocket implant is often used to prevent source/drain punch through in NMOS (n-channel) transistors. It serves to block unintended electrical connections between the source and drain regions in these devices.
How are the gate sidewall spacers formed in the source/drain module, and what functions do they serve in the semiconductor fabrication process?
The gate sidewall spacers are formed by depositing conformal silicon nitride (or CVD oxide) using LPCVD and then subjecting it to an unpatterned anisotropic RIE (Reactive Ion Etching). These spacers function as a mask for the source/drain implants and as a barrier for subsequent silicide formation.
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