How you will take care of power in standard cells?

Depending on the width(or pitch) of the metal layers the metal layer definition is defined for Standard cells.

Lower metals like M0, M1, M2, and M3 are the layers used for designing the std cells, In Physical Design, we use them for power routing as well as signal routing purposes, and These layers are also called DPT layers. (only in lower nodes>16nm). The upper layers are used for routing purposes (power+signal+clock).

After certain layers, we will not route (signal routing) the design. The above layers are totally used for power. (IR drop +EM are the two things we consider for the power grid). The number of layers is depending on the design and foundry. The layer stack definition defines the layer’s information. The lower metals possess higher resistance and the higher(top) metal layers Retain a lower resistance.

The reason for deciding on metal width  is 

(R=rho*L/A)

The resistance is depending on the following factors

R=Resistance in ohms

Rho=Resistivity In ohms

L=Length in m

A=cross sectional area of m^2