Isolation cells must connect input pins to logic ‘0’ to prevent floating input pins in a powered block. In VLSI, isolation cells are also referred to as clamp cells. Specific isolation cells are typically used for this purpose and these cells are available in most physical IP libraries today
Isolation logic must be inserted at the interfaces of power-gated blocks such that the logic in these blocks is isolated from the rest of the design during the shutdown.
Level Shifter cells
The design of a level shifter to provide an effective voltage swing between one different voltage rails is an analog design problem. And for analog design reasons, these cells are typically only designed to shift one direction – either from a higher voltage to a lower one, or from a lower voltage to a higher one. Types of Level Shifters are following
Level shifters are inserted automatically during synthesis once the location and usage rules have been defined.
High to Low-Level Shifters
High to Low-Level shifters are used for signals crossing from the higher voltage domain to the lower voltage domain. Although it is not necessary to use a level shifter when signals are crossing from a higher voltage domain to a lower voltage domain because the signals will be correctly interpreted in the destination domain, we usually do so to prevent stress on the transistors in the lower voltage domain caused by the high voltage of the source signal.
Low to High-Level Shifters
If specialized high-to-low-level shifter cells were not provided in the library, the entire library would have to be re-characterized to allow accurate static timing analysis. Each gate would have to be characterized for an arbitrary input voltage swing. As shown in Figure 1, high to low-level shifters can be quite simple, essentially two inverters in a series. As implied by the drawing, a high-to-low-level shifter only introduces a buffer delay, so its impact on timing is small.
The retention cells are used to retain the state of key registers during the power-off state.
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