Extraction from Layout: Device Extraction and Parasitic Extraction
Device Extraction
Device extraction is a crucial step in integrated circuit design. It involves the process of extracting the circuit or netlist from the drawn layout. This extraction is necessary for various purposes, including:
Layout vs. Schematic (LVS) Checks: To ensure the correctness of the layout, the extracted circuit must be compared against the original schematic design.
Power Analysis: Understanding and analyzing the power consumption of the circuit.
Timing Analysis: Evaluating the timing behavior and delays within the circuit.
Signal Integrity Analysis: Assessing the quality and integrity of signals as they traverse the circuit.
To perform device extraction, information about the devices is obtained from the layout’s geometry and layer data. For example, if there is an overlap between the poly-silicon and n-diffusion layers, it indicates the formation of an nMOS (n-channel Metal-Oxide-Silicon) transistor. Similarly, if poly-silicon overlaps with a p-diffusion layer within an n-well layer, it forms a pMOS (p-channel Metal-Oxide-Silicon) transistor. Additionally, information about connectivity is determined from the metal and contact layers.
Parasitic Extraction
In VLSI (Very-Large-Scale Integration) circuits, interconnect lines, which are used to connect the output of one component (driver) to the input of another (load), introduce parasitic effects such as resistance and capacitance. Among these, parasitic resistance and capacitance are the most significant.
Parasitic resistance is a measure of the resistance encountered by electrical signals as they pass through interconnect lines.
Parasitic capacitance is a measure of the capacitance that exists between adjacent conductive traces in the interconnect.
To estimate the impact of these parasitic effects accurately, they must be quantified based on the geometry information of the layout and material properties. This process of determining the resistance and capacitance values from geometry and material properties is known as parasitic extraction.
In summary, extraction from layout involves two main processes: device extraction, which focuses on deriving the circuit or netlist from the layout for various design and analysis purposes, and parasitic extraction, which is essential for understanding and mitigating the impact of parasitic resistance and capacitance in interconnects within VLSI circuits.