Forum › Tag: ESD Protection Layout Select statusStartus:AllOpenResolvedClosedAnsweredUnansweredSelect categoryAllCMOSLayoutMemory LayoutPhysical DesignQuestionsRTL DesignStandard Cell Sort byViewsAnswersVotesHow would you handle ESD protection layout when the IO pad shares space with analog signal routing?AnsweredCircuitCreator answered 3 months ago • Layout394 views1 answers0 votes
CircuitCreator
By siliconvlsiBy siliconvlsi