Forum › Tag: Inductance Path In Layout Select statusStartus:AllOpenResolvedClosedAnsweredUnansweredSelect categoryAllCMOSLayoutMemory LayoutPhysical DesignQuestionsRTL DesignStandard Cell Sort byViewsAnswersVotesHow do you place high-frequency decoupling caps in layout without introducing unwanted inductance paths?Opensiliconvlsi asked 8 months ago • Physical Design491 views0 answers0 votes