Why is using dummy poly in some standard cell rows considered harmful in FinFET nodes?

The main issue is parasitics. Dummy poly in some rows can add unexpected capacitance or coupling, especially in dense FinFET layouts. For instance, an extra dummy line near a signal path may increase delay or noise. That’s why foundries usually recommend uniform poly density rules instead of mixing dummy and non-dummy rows.

Dummy poly can be harmful in FinFET nodes because it changes the stress and uniformity of fins. In older planar nodes, dummy poly was fine for density, but in FinFETs, even a small change in stress can shift device characteristics. For example, it may cause mismatch between two transistors that should behave the same.