Sanity checks before going to start Physical Design step

Physical design engineers must perform sanity tests on VLSI designs to guarantee that the inputs are accurate and consistent. Any mistakes in the input files could lead to issues later.

What are the sanity checks in PD?

List of sanity checks

1. Check_Libaray#
2. Check_Netslist
3. Check_SDC
4. Check_design
5. Report_QOR
6. Report_constraint
7. Report_timing

Library Check

In short, a library check involves confirming that the physical and logical libraries are consistent before beginning the physical design. Additionally, it evaluates the two libraries’ quality and notes any errors. The logical and physical libraries must both contain the cells used in the design.

Netlist Check

This check examines the netlist that is currently loaded and flags any inconsistencies. Netlist check mostly examines#

1. Floating input pins and nets.
2. Multidrive nets.
3. Mismatch pin.
4. Unloaded outputs.
5. Uncontraints pins.
6. No direct connection between VDD and VSS.

SDC Check

Before beginning the design, the SDC file must be verified. The following are a few of the SDC file’s prevalent problems.

1. Multiclock driven registers
2. Slew or load constraint
3. Missing clock definition
4. Unconstrained path
5. Input/output delay missing for a port
6. The clock is reaching all synchronous elements.