To understand these let’s take the example of PMOS’s current source. The drain current of the source depends on the Gate to source voltage (Vgs) of the PMOS, where the source of connected to VDD. Now If we shield the Gate node with VSS, the noise in the VSS net will couple to the gate and this will change Vgs, and the current will change. Instead, if we shield the gate with VDD, even if VDD changes slightly, Vgs will remain constant and so is the current.
|Analog Layout Design Interview Questions||Memory Design Interview Questions|
|Physical Design Interview Questions||Verilog Interview Questions|
|Digital Design Interview Questions||STA Interview Questions|