The self-aligned silicide (salicide) module is a crucial step in semiconductor manufacturing, particularly at the boundary between the Front-End-of-Line (FEOL) and Back-End-of-Line (BEOL) processes. Its primary purpose is to reduce the sheet resistance of both the polysilicon and active silicon regions, enhancing the electrical conductivity of these areas.
Silicide formation process
Here’s a simplified explanation of the silicide formation process:
- Choice of Metal: Typically, metals like titanium or cobalt are chosen for silicide formation. These metals have the property that they will not readily form silicide over dielectric materials like silicon nitride.
- Metal Deposition: The selected metal, such as titanium or cobalt, is deposited uniformly over the entire silicon wafer’s surface. This is often done using a technique like sputtering.
- Nitride Cap: To minimize contamination and ensure the metal’s proper reaction with silicon, a thin layer of titanium nitride (TiN) is deposited as a cap over the metal layer.
- Annealing Process: The wafer is subjected to a relatively low-temperature annealing process in a nitrogen ambient environment. This step facilitates the reaction between the deposited metal (e.g., titanium or cobalt) and the underlying silicon, forming a type of silicide known as TiSi2 (for titanium) or CoSix (for cobalt). It’s important to note that the resulting silicide (in this case, the C49 phase) has relatively high resistivity.
- Blocking Effect of Nitride and Oxide: The silicon nitride and silicon oxide layers below the metal act as barriers during the annealing process. They prevent silicide formation on the sidewalls of structures and inside trenches.
- Two-Step Annealing: To prevent unwanted overgrowth of the silicide, which could lead to leakage currents, a two-step annealing process is used. The first anneal, as described above, forms the high resistivity phase (C49). Importantly, this phase change doesn’t occur on the nitride.
- Etching Unreacted Metal: After the first anneal, any unreacted titanium or cobalt is removed from the wafer’s surface through wet chemical etching.
- Second Anneal: The wafer undergoes a second rapid thermal annealing (RTA) process, this time at a slightly higher temperature and in an argon ambient atmosphere. This step converts the high resistivity phase (C49) into the desired low resistivity phase (C54 for TiSi2), significantly improving electrical conductivity.
In summary, the silicide module is a sophisticated process that enhances the electrical properties of silicon regions by forming a low-resistivity silicide. It involves careful control of temperature, materials, and annealing steps to achieve the desired electrical characteristics while preventing unwanted side effects like overgrowth and contamination.
What is the primary purpose of the self-aligned silicide module in semiconductor manufacturing?
The self-aligned silicide module is used to lower the sheet resistance of both the polysilicon and active silicon regions in semiconductor devices, improving their electrical conductivity.
Why is it important for metal silicide not to form over dielectric materials like silicon nitride in the silicide process?
Metal silicides should not form over dielectric materials like silicon nitride to prevent unintended electrical connections and to ensure that the silicide formation is confined to specific regions of the semiconductor device.
What metals are commonly used in the silicide process, and how are they deposited onto the wafer surface?
Metals such as titanium or cobalt are commonly used in the silicide process. These metals are deposited onto the entire wafer surface, often with a thin layer of TiN (titanium nitride) as a cap, using techniques like sputtering.
Why is it necessary to perform two separate anneals in the silicide process, and what potential issue does this approach prevent?
Two separate anneals are performed to prevent spacer overgrowth of the silicide. The first anneal forms the high resistivity phase without the risk of silicide formation on the nitride. The second anneal occurs after wet chemical etching to achieve the low resistivity phase. This approach prevents excessive overgrowth, which could lead to leakage current between the source, drain, and gate of the transistors.
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