Skew refers to the difference in arrival times of signals at different points in a circuit. It is the delay or phase shift between the arrival times of a signal at one location and the arrival time of the same signal at another location in the circuit.
Skew is frequently brought on by variations in the paths that the signals take, which may be brought on by changes in wire lengths, gate delays, or other elements.
Skew can be a serious problem in high-speed circuits, especially those that run at GHz clock rates. High skew can result in issues like setup and hold violations, which may latch wrong data into flip-flops or other storage components. Designers use methods like careful routing and clock tree synthesis to reduce skew and make sure that signals arrive at their destinations within the necessary timing windows in order to avoid these problems.
Positive Clock Skew
In Positive Clock Skew, the clock signal arrives at a destination later than it arrives at its source. In other words, the clock signal is delayed by different amounts in different parts of the circuit, resulting in a phase shift between clock signals at different locations.
Positive clock skew is a frequent issue, particularly in high-speed circuits with lengthy interconnects or variable gate delays. Data that is latched too early or too late can result in setup violations or hold violations, respectively.
How to Solve Positive Clock Skew?
The clock delay is equalized throughout the circuit by designers using methods like clock tree synthesis and buffer insertion to reduce positive clock skew. To modify the phase of the clock signal and correct for any lingering skew, they can also employ delay-locked loops (DLLs) or phase-locked loops (PLLs). Overall, to ensure good operation and timing in high-speed circuits, clock skew must be minimized
Negative Clock Skew
In Negative Clock Skew, the clock signal arrives at a destination earlier than it arrives at its source. In other words, the clock signal is advanced by different amounts in different parts of the circuit, resulting in a phase shift between clock signals at different locations.
With high-speed circuits, negative clock skew can also be problematic, especially if it results in hold violations or too-late latching of data. Negative clock skew, however, can occasionally be advantageous as it helps lessen setup violations and give the data more time to stabilize before being latched.
How to Solve Negative Clock Skew?
Designers may employ strategies similar to those used to reduce positive clock skew, like clock tree synthesis and buffer insertion, to reduce negative clock skew. To correct the phase of the clock signal and make up for any lingering skew, they may additionally use DLLs or PLLs. Overall, to maintain dependable functioning and timing in their circuits, designers must carefully balance the trade-offs between positive and negative clock skew.#
Clock skew refers to the timing variation or mismatch between two clock signals, typically the main clock (CLK) and its complement (CLK). It’s an important consideration in digital circuit design as it can significantly impact the operation of registers and other clock-dependent elements. Here’s how clock skew can affect registers:
Clock Overlap
In an ideal scenario, CLK and CLK are perfectly inverted signals, with zero delay between them. However, in practice, variations can occur in the clock signal paths, including routing delays and load capacitance changes due to connecting latches. These variations can lead to clock skew, causing CLK and CLK to overlap, as shown in Figure 7.20b.
Race Conditions
When CLK and CLK overlap, it can result in race conditions within registers. For example, consider a negative edge-triggered register. During the clock’s rising edge, the slave stage should enter a hold mode and stop sampling the master stage’s output. However, due to clock overlap, both sampling pass transistors conduct, creating a direct path from the input (D) to the output (Q). This allows data at the output to change on the rising edge of the clock, which is undesirable and can lead to metastable states where the output’s value depends on system noise.
Undefined States
Clock skew can also create undefined states in registers. For instance, in a multiplexer-based register, if CLK and CLK overlap, a node (e.g., node A) can be driven by both the data input (D) and another signal (e.g., B). This overlapping drive can lead to unpredictable outcomes and incorrect data storage.