SOC Design Synthesis
Behavioral synthesis, also known as architectural synthesis or high-level synthesis, encompasses the process of identifying the architectural resources required to implement the design resources corresponding to the behavioral representation of a System-on-Chip (SOC) design. This involves binding available standard cells, memory hard macros, and other IP macro resources to the functional behavior while establishing the execution sequence or order.
In achieving a high-performance netlist representation for SOC design, the strategy for synthesis should consider several key factors:
- The complexity of the SOC
- The number of design cores within the SOC
- The types of cores (soft, hard, netlist)
- The computational capability of the system running the synthesis
- The debugging capability of the designer
For highly complex SOC designs, it’s advisable to conduct synthesis with multiple levels of hierarchy. This approach retains module names and facilitates easier debugging of logic equivalences. The synthesis tools can generate a netlist in either hierarchical form, maintaining the input file’s hierarchy levels, or in flat netlist form where the entire design hierarchy is collapsed into a single level. Conversely, SOC designs of lower complexity are synthesized in a single execution, with all modules at the same hierarchical level. This is referred to as flat synthesis, resulting in a gate-level netlist where instances of various standard cells are interconnected. Debugging flat netlists can be challenging and time-consuming.
In hierarchical synthesis, each block/module-level design is synthesized individually according to the designer’s hierarchy, and the resulting block-level netlists are brought together with the top-level module to generate the hierarchical or flat netlist as needed. When incorporating cores available as netlists, the final netlist is updated. If hard cores are integrated, they appear as black boxes with interface connections but without functionality. Therefore, designers need a comprehensive understanding of the entire SOC’s instances. The synthesis SDC (Synopsys Design Constraints) file is also produced, which is used alongside the netlist for Static Timing Analysis (STA) and physical design tools.
During the synthesis process, all flip-flops in the design are replaced with scan flip-flops from the library to enable Design for Testability (DFT) activities. To ensure effective SOC design optimization, it’s crucial to guide the synthesis tool through the SDC file, directing it to use a specific set of standard cells while restricting the use of certain low-drive cells. A mix of high-performance logic cells from the same library can also be applied based on design objectives. An example of this is the utilization of low and high-VT cells for appropriate modules to achieve a low-power netlist.
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