SPICE Netlist

A SPICE netlist is a text-based representation of a circuit. Viewing the netlist helps you to learn about SPICE syntax and simulation.

SPICE netlist for the CMOS inverter

M1 Y A VDD VDD PMOS W=5U L=0.18u
M2 Y A 0 0 NMOS W=2U L=0.18u
CL Y 0 0.1PF
VDD VDD 0 1.8V
VIN A 0 PULSE 0 1.8V 0N 1N 1N 5N 10N
.TRAN 0.01N 20N
.PRINT TRAN V(A) V(Y)
.PLOT TRAN V(A) V(Y)
.END

SPICE netlist to design a two-input CMOS NAND gate

MP1 VDD A OUT VDD PMOS W=1u L=0.18u
MP2 VDD B OUT VDD PMOS W=1u L=0.18u
MN1 OUT A N1 VSS NMOS W=1u L=0.18u
MN2 N1 B VSS VSS NMOS W=1u L=0.18u
VDD VDD 0 1.8
VSS VSS 0 0
VA A 0 PULSE 0 1.8 0n 1n 1n 3n 10n
VB B 0 PULSE 0 1.8 0n 1n 1n 8n 20n
CY OUT 0 0.1pF
.TRAN 1p 40n
.PLOT TRAN V(A) V(B) V(OUT)
.END

SPICE netlist to design a two-input CMOS NOR gate

MP1 VDD A N1 VDD PMOS W=1u L=0.18u
MP2 N1 B OUT VDD PMOS W=1u L=0.18u
MN1 OUT A VSSVSS NMOS W=1u L=0.18u
MN2 OUT B VSS VSS NMOS W=1u L=0.18u
VDD VDD 0 1.8
VSS VSS 0 0
VA A 0 PULSE 0 1.8 0n 1n 1n 3n 10n
VB B 0 PULSE 0 1.8 0n 1n 1n 8n 20n
CY OUT 0 0.1pF
.TRAN 1p 40n
.PLOT TRAN V(A) V(B) V(OUT)
.END