STA Interview Questions for VLSI Interviews(2025)
Static timing analysis (STA) is a technique for evaluating the timing performance of a design. Here we will see some basic interview Questions for STA in the Physical design Domain.
What are the important features of STA?
What are the major functions of STA?
What is Net Delay?
What are the OCV & AOCV?
Significance of CRPR in Static Timing Analysis
What are the different types of delays in ASIC or VLSI design?
During static timing analysis, what are the ideal characteristics of a clock?
What do you mean by positive, negative, and zero slack?
What is synchronous reset along with its advantages and disadvantages?
10 Ways To Fix Setup and Hold Time Violations
How STA is different from circuit simulation?
Which input files are required to run STA?
How will you measure slack for setup and hold time?
What is Clock Latency?
List of Sanity Checks in Physical Design
For timing analysis, what are the various paths that the designer considers?
Which type of jitters can be used to determine high-frequency jitter?
What do you understand by time stealing?
List the types of delay models used to estimate the delay.
Difference between statistical and conventional STA
When Static Timing Analysis is done?
How STA is performed on the circuit?
What do you mean by Launch and capture edge?
How does the clock skew violate setup and hold time constraints?
What are the main reasons for setup or hold time violations?
What are reset assertion and reset Deassertion?
What is the difference between time-borrowing and time-stealing?
What do you mean by critical path, false path, and multicycle path?
What do you mean by timing path? What are the start and endpoints?
How many types of clock jitter are there?
What are the effects of Metastability?
Global on-chip variation
Local on-chip variation
What are the various timing paths?
What do you mean by clock skew?
What is positive, negative, and zero clock skew?
What is Overshoot and Undershoot Glitch
How to Find the Setup for Flip-Flop
Low Power Design Techniques Used in Physical Design
DIBL GIDL BTBT and Tunneling Effect in CMOS Devices
i/p’s and o/p’s of power planning and placement
What is the odd cycle error in VLSI
List the parameters on which net delay or cell delay depends.
Temperature Inversion on Lower Nodes
Duty Cycle & Pulse Width
What are the inputs of LVS?
What is the content in the .lib, .lef & .tlef files
How to fix setup and hold violations at a time?
Difference between the clock mesh and clock tree-type distribution system
Input skew and output skew
Process Corners in VLSI
What is SPICE Netlist
Different Types of IC Packaging
What are the steps involved in semiconductor device fabrication?
What is the feedback in VLSI?
Process Variation in VLSI
Which parameters decide the Spacing between Macros
What is Dynamic Power?
Positive and Negative Clock Skew
Why timing analysis is an important factor?
Why do we go for FinFET?
How does FinFET reduce leakage?
What is better than FinFET?
Where is FinFET technology used?
What do you mean by reset?
How many types of resets are available?
Explain the concept of Asynchronous Reset.
Which factors decide setup time and hold time?
What are the main characteristics of the time-borrowing concept?
What are the worst paths and best paths?
Ways to Fix the Timing Path
Is the term clock skew and global skew the same?
What is a false path in static timing analysis?
Out of setup time violation and hold time violation, which is more dangerous to the design specifications and working mode?
List the ideal conditions for the timing path.
How will you calculate negative and maximum borrow time?
What do you mean by clock Jitter?
