Challenges in Modern SoC Design Verification
However, when we’re working on SoC design, we face several challenges that we need to overcome to succeed. You might encounter these challenges from different angles, such as the complexity of the design itself, the need to integrate various components, and meeting specific performance and power requirements.
Electrical Rule Checking (ERC)
SoC design teams face the formidable challenge of taping out projects with functioning silicon on the first attempt, without encountering any bugs. This goal necessitates rigorous checking and verification at various levels of design to prevent bugs from creeping in. These checks span from the system level down to the physical layout level, encompassing RTL, gate, and transistor levels. However, during the process of Electrical Rule Checking (ERC), formal tools may erroneously flag false positives, which are errors that shouldn’t have been reported, while missing out on real design errors, termed as false negatives.
Read also: What is Concepts of Analog Layout?
Aniah : The EDA Company
Aniah, a newer EDA company, has developed a specialized ERC tool called OneCheck to address these challenges. OneCheck employs formal methods and intelligent clustering of errors to ensure the correctness of IC designs at the transistor level. This tool can be applied at various stages of the IC flow to verify both analog and digital circuitry, thereby detecting common design flaws such as missing level shifters, floating gates, high impedance states, floating bulk, diode leakage, and electrical overstress.
False errors encountered during ERC
One of the key features of OneCheck is its capability to handle four typical classes of false errors encountered during ERC:
Topology Specific: OneCheck employs pseudo-electrical analysis to model voltages and currents, enabling the detection of topology-related false errors like missing level shifters.
Analog Path: Users can identify and filter false errors related to analog paths using OneCheck, irrespective of current or voltage reference nets.
Impossible Path Logically: The tool identifies all tree-like paths utilized by analog multiplexors, facilitating the rapid rejection of thousands of false errors.
Missing Supply in Setup: OneCheck clusters all errors associated with a missing supply together, simplifying the process of updating the power supply setup.
Moreover, OneCheck does not rely on vectors and verifies all circuit states in a single run, making it highly efficient. It can be integrated into the design workflow right from the initial schematic netlist entry stage, even before any simulations are conducted. Despite the complexity of circuits, OneCheck demonstrates fast run times, typically taking only a few seconds for mixed-signal designs with millions of transistors and numerous power scenarios.
In summary, Aniah’s OneCheck tool provides a reliable solution to the challenge of false errors in ERC, offering chip design teams a valuable resource to ensure first silicon success and mitigate the risk of design flaws before manufacturing. This advancement in formal technology addresses the limitations of traditional ERC tools, making it a valuable asset in the design community
Source: Electrical Rule Checking and Exhaustive Classification of Errors