Explain the term metastability.
The setup and hold time violation in a flip-flop causes the metastable or quasi-stable state, which is an unexpected state. Digital equipment like FPGA, ASIC, etc. may experience system failure as a result. The system operation will be further compromised if the circuit in the metastable condition is unable to settle at either logic 0 or logic 1 within the allotted time frame. It occurs as a result of the flip-flop switching during the clock transition.
Therefore, this circumstance is known as metastability when setup and hold time are broken and the flip-flop output inside the FPGA is unknown or uncertain.
What are the effects of metastability?
- The circuit will draw excessive current.
- The circuit does not meet timing constraints.
- The output will have non-deterministic behavior.
- The output of the clocked pass gate does not charge properly.#
- The circuit will enter a metastable condition and the flip-flop will mistakenly toggle if fan-out is high. The system will act in an unanticipated manner.
You may also like the following post
- CMOS Interview Questions
- What is the Time Borrowing Concept?
- Difference between the TTL chips and CMOS chips?
- Memory Circuit and Layout Design Interview Question