What do you mean by reset?
The parameter used to initialize the circuit is reset. Resetting hardware forces it into a known state since it lacks the ability to self-initialize. Reset initiates the circuit’s startup during simulation, while reset activates the circuit in real hardware.
How many types of resets are available?
What is synchronous reset along with its advantages and disadvantages?
The synchronous reset will be used when a designer needs a complete synchronous circuit, which has no metastability or clock glitch issues. Because of the synchronous reset, it is sampled in time with the clock. Till the clock edge is high, the synchronous reset won’t be engaged. Stretching the reset will make it visible during the clock signal.#
Advantages of Synchronous Reset
- The synchronous circuit is fully completed.#
- The problem of clock glitches is reduced.
- Deassertion will occur in a single clock, ensuring that the reset recovery time requirements are met.
Disadvantages of Synchronous Reset
- It makes the process slow.#
- A clock signal must be present always.
- It is not suited for clock-gated circuits.
- The reset signal should be wide enough to be visible through the clock signal.
Explain the concept of Asynchronous Reset.
The asynchronous reset will be used when the chip needs to be powered up before the clock signal. As soon as the reset signal is high or enabled, an asynchronous reset will be initiated. It is independent of the signal from the clock. The clock signal doesn’t need to be awaited.#
Advantages of Asynchronous Reset
- It makes the process faster.#
- No need to wait for the clock signal.
- Reset has the highest priority.
Disadvantages of Asynchronous Reset
- Metastability may occur.#
- Chances of clock glitches may occur.
What are reset assertion and reset Deassertion?
Reset Assertion is Active apply the reset means when the reset signal is logically true. During an asynchronous reset, the reset assertion and de-assertion should meet the minimum required pulse width. Reset De assertion is The release of reset means when the reset signal is logically false.
During asynchronous reset, the de-assertion may cause metastability because it may be the case that some flip-flops come out of reset before others. During an asynchronous reset, the reset assertion and de-assertion should meet the minimum required pulse width.#
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