Routing in VLSI involves the creation of physical connections between signal pins using metal layers. It is an important step that follows Clock Tree Synthesis (CTS) and optimization, as it determines the precise pathways for interconnecting standard cells, macros, and I/O pins. The layout process establishes electrical connections using metals and vias, which are based on the logical connections in the netlist, converting logical connectivity into physical connectivity.
CTS encompasses information about all the cells, blockages, clock trees, buffers, inverters, and I/O pins incorporated into the design. The Routing program utilizes this data to establish all the required connections defined in the netlist, ensuring the absence of any Design Rule Check (DRC) violations. By making these connections, the tool ensures that:
The design is completely routed.
Congestion hotspots are either absent or minimized.
Timing DRCs (Design Rule Checks) and Quality of Results (QOR) are met.
There are minimal violations of Layout versus Schematic (LVS) and Signal Integrity (SI).
The mechanism of routing in VLSI involves the establishment of specific pathways for interconnections, including regular cell and macro pins, block boundary pins, and chip boundary pads. The tool incorporates information about the precise placements of blocks, block pins, and I/O pads at the chip borders after placement and CTS. It also utilizes the logical connections defined by the netlist. The routing stage employs metal and vias to construct the necessary electrical connections in the layout. Furthermore, the program relies on “Design Rules Checks (DRC)” to ensure proper linkages.
The steps involved in routing in VLSI are as follows:
Global Route: The global route assigns nets to specific metal layers and global routing cells. The objective is to avoid congested global cells while minimizing diversions. Global routes also steer clear of pre-routed P/G (Power/Ground) connections, placement issues, and routing bottlenecks.
Track Assignment (TA): This step allocates each net to a specific track and lays down the actual metal traces. It aims to create long, straight lines to minimize the number of vias. Physical DRC is not taken into account at this stage.
Detail Routing: Detail routing addresses any DRC violations that arise after track assignment. It uses small regions (SBoxes) of a fixed size to repair these violations. Detail routing progresses through the entire design, box by box until the routing process is complete. It also incorporates timing-driven routing techniques.
In conclusion, if you are interested in learning more about VLSI design, you can enroll in one of the online VLSI courses offered by Chipedge, a leading VLSI training institute in Bangalore. They provide a wide range of courses, including design verification courses and RTL design courses. For further information, please feel free to contact them.
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