Useful Skew: Useful skew, also known as intentional skew or controlled skew, refers to the intentional introduction of small and controlled variations in clock arrival times to improve the timing characteristics of a circuit. It is a technique employed during clock tree synthesis (CTS) to balance the clock distribution and mitigate the effects of inherent process variations.
By introducing controlled delays or advances in the clock paths, useful skew helps equalize the arrival times of clock signals at critical points in the design. This technique compensates for process variations and reduces the impact of clock skew on the timing performance of the circuit.
Useful skew is used to achieve better clock synchronization, reduce setup and hold time violations, and improve the overall performance and reliability of the integrated circuit.
Local Skew: Local skew refers to the variation in clock arrival times within a localized region or specific clock domain of the integrated circuit. It represents the skew between different clock sinks (elements that receive the clock signal) within a particular region or module.
Local skew is influenced by factors such as interconnect delays, buffer placements, and load variations within the specific clock domain. It can affect the setup and hold time requirements between different sequential elements in the same domain.
During clock tree synthesis, efforts are made to minimize local skew by optimizing the placement and sizing of buffers, adjusting the routing of clock lines, and applying useful skew techniques.
Global Skew: Global skew refers to the variation in clock arrival times across the entire integrated circuit, encompassing multiple clock domains and clock sinks. It represents the skew between different clock domains or regions within the design.
Global skew is influenced by factors such as the length and routing of the clock distribution network, process variations, and the overall complexity of the design. It can impact the synchronization and timing relationships between different clock domains.
To minimize global skew, advanced clock distribution techniques are employed during the physical design phase. These techniques include proper buffer placement, clock tree optimization, and the use of clock mesh structures.
Useful skew refers to the intentional introduction of controlled variations in clock arrival times to improve timing characteristics and mitigate process variations.
Local skew represents the variation in clock arrival times within a specific clock domain or a localized region of the design.
Global skew represents the variation in clock arrival times across multiple clock domains or regions of the integrated circuit.