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Home»Analog Design»Why bias voltage for PMOSFETs are referred to shield with VDD? Why not VSS?
Analog Design

Why bias voltage for PMOSFETs are referred to shield with VDD? Why not VSS?

siliconvlsiBy siliconvlsiMarch 12, 2022Updated:May 12, 2024No Comments1 Min Read
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Why bias voltage for PMOSFETs are referred to shield with VDD
Why bias voltage for PMOSFETs are referred to as shield with VDD

To understand these let’s take the example of PMOS’s current source. The drain current of the source depends on the Gate to source voltage (Vgs) of the PMOS, where the source of connected to VDD. Now If we shield the Gate node with VSS, the noise in the VSS net will couple to the gate and this will change Vgs, and the current will change. Instead, if we shield the gate with VDD, even if VDD changes slightly, Vgs will remain constant and so is the current.

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