DRAM (Dynamic Random Access Memory)
DRAM is widely used in digital electronics where low-cost and high-capacity memory is required. One of the largest applications for DRAM is the main memory in modern computers.
4-transistor DRAM Architectures
The DRAM (Dynamic Random Access Memory) structure shown in Figure 1(a) utilizes four nMOS (negative-channel metal-oxide-semiconductor) transistors. In this design, binary data is written in complemented form by enabling the word line, and it’s stored in the parasitic storage capacitances.
However, there’s no restoring path from VDD (the power supply voltage) to these capacitances, which means the stored charge tends to leak away over time. Therefore, to retain the logic level, these capacitors must be periodically refreshed. During the read operation, the word line is enabled, and the stored data becomes available at the bit lines in both its true and complemented forms.
3-transistor DRAM Architectures
In the 3-transistor DRAM architecture illustrated in Figure 1(b), there are three nMOS transistors involved. Here, only M2 is used to store binary data, utilizing its parasitic gate capacitance. During the write mode, the write word line is enabled, allowing the logic from the write bit line to be transferred to the parasitic storage capacitance. In the read mode, the read word line is enabled, and the complement of the stored data becomes available in the read bit line.
1-transistor DRAM Architectures
The 1-transistor DRAM cell, often employed in high-density DRAM architectures, consists of a dedicated storage capacitor, as depicted in Figure 1(c). During the write operation, the word line is enabled, allowing data from the bit line to be stored in the capacitor. When it comes to the read operation, the word line is again enabled, and the stored data becomes accessible at the bit line.
