Best Practice for Analog Layout Design Here are some best practices for analog layout design: Start with a good floorplan:…
Author: siliconvlsi
NWELL Antenna Effect The NWELL antenna effect is a phenomenon that can occur in CMOS (Complementary metal-oxide-semiconductor) circuits when the NWELL…
Fin Field-Effect Transistor FinFET (Fin Field-Effect Transistor) is a type of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) that uses a thin, vertical…
Why do we use p substrate in CMOS? Starting with a p-type substrate allows one to build n-channel transistors without…
What are Resistance Capacitance and Inductance? Resistance Capacitance and Inductance are primary components of an Electric circuit. Resistance All materials…
Triple-Well Processes Triple-Well Processes are used to isolate the most sensitive circuit in Analog Layout Design. A triple-well structure contains…
CMOS Process Integration: FEOL & BEOL The CMOS process integration is often divided into two major parts: the front end…
SPICE Netlist A SPICE netlist is a text-based representation of a circuit. Viewing the netlist helps you to learn about SPICE syntax…
Process Variation in VLSI Process Variation in VLSI is related to PVT(Process Voltage and Temperature). The lateral dimension, doping concentration,…
On-chip variation (OCV) is a recognition of the intrinsic variability of semiconductor processes and their impact on factors such as logic…