Sanity checks before going to start Physical Design step Physical design engineers must perform sanity tests on VLSI designs to…
Browsing: Physical Design
Addressing Clock Tree Synthesis Challenges In order to equalize the clock delay to all clock inputs, the Clock Tree Synthesis…
If a design has both IR drops and congestion, there are a few potential solutions to fix the issue, Spread…
Difference between statistical and conventional STA Statistical static timing analysis (SSTA) and conventional static timing analysis (STA) are both techniques…
Impact of Metastability on Digital Circuits The setup and hold time violation in a flip-flop causes the metastable or quasi-stable…
What is CRPR in VLSI? The name “CRPR,” or clock reconvergence pessimism removal, is used in static timing analysis. Based…
Clock mesh and Clock tree-type distribution system Clock mesh technology provides uniform, low-skew clock distribution and offers better tolerance to…
What are the i/p’s and o/p’s of power planning? Power planning means making sure that all of the design’s macros,…
What is an always-on cell in VLSI? An always-on cell (AON) in VLSI is a type of digital circuit that…
NWELL Antenna Effect The NWELL antenna effect is a phenomenon that can occur in CMOS (Complementary metal-oxide-semiconductor) circuits when the NWELL…