CMOS Process Options
To implement both NMOS- and PMOS-FETs in semiconductor processes, it’s necessary to have areas of p-conductive and n-conductive bulk. This can be achieved through various techniques, as illustrated in Figure 1, with the example showing a p-doped substrate (colored in red). Note that the same principles apply for n-doped substrates.
Initially, the raw wafer is doped as a common bulk for one type of transistor, either NMOS or PMOS. This means that the bulk areas for the other type must be created by selectively redoping the substrate. This can be done through techniques like diffusion or implantation followed by diffusion, which result in the formation of specific regions called “wells.” This approach is known as a single-well process, as shown on the left side of Figure 1.
Threshold Voltage Variation
One challenge with single-well processes is that NMOS and PMOS transistors tend to have different threshold voltage values. This difference arises because redoped areas inherently have a higher dopant concentration than before redoping. This results in a different tilt angle on the “p–n scale” for the NMOS and PMOS regions, leading to different threshold voltages. Ideally, circuit design benefits from symmetrical threshold voltages.
To address the varying threshold voltages in single-well processes, a technique called “threshold-adjust” implantation is often employed. This involves implanting just enough acceptors across the whole wafer without using a mask. The aim is to equalize the threshold voltages of PMOS and NMOS FETs by modifying the dopant concentration. While this aligns the threshold voltages, it may reduce the hole mobility in PMOS-FETs due to the increased number of dopant atoms.
To achieve greater control and symmetry in threshold voltages, twin-well processes are commonly used. In this approach (center of Figure 1), the backgates for both NMOS and PMOS FETs are created as separate wells in the semiconductor process. This allows for precise adjustment of dopant concentrations for each type, ensuring symmetrical threshold voltages. Despite the need for an extra masking step, twin-well processes are widely favored.
For applications requiring even more flexibility, triple-well variants (right side of Figure 1) are available. Here, one of the two back gate regions is produced by doping twice, effectively creating a “well within a well.” This introduces additional degrees of freedom, including the ability to set the back gates for both transistor types at any potential by reverse biasing the p–n junctions. Such processes are valuable in applications like automobile electronics, where high voltages are involved.
In summary, the choice of semiconductor process depends on factors like the desired threshold voltages, symmetry, and flexibility required for a specific application, with single-well, twin-well, and triple-well processes offering varying levels of control and customization.
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