**What Is Noise Margin in VLSI**

Noise margins represent the difference between the minimum voltage level that represents a logic high (logic ‘1’) and the maximum voltage level that represents a logic low (logic ‘0’). They define the voltage range within which a circuit can correctly interpret and distinguish logic levels. In other words, noise margins provide a buffer zone to account for variations in signal levels caused by noise.

**Types of Noise Margins**

There are two main types of noise margins in VLSI design: the noise margin for a logic high (NMH) and the noise margin for a logic low (NML). NMH is the difference between the minimum voltage level for a logic high and the maximum voltage level for a logic low. That is, both NMH and NML can be expressed as follows.

NMH = VOH − VIH

NML = VIL − VOL

Four voltage levels are established to indicate input and output voltage values, allowing two logic circuits of the same or different families to be cascaded while tolerating process, voltage, and temperature (PVT) fluctuations. The input logic 0 and 1, respectively, are specified by the two input voltage levels VIL and VIH. The output logic 0 and 1.1 are specified individually using the two output voltage levels VOL and VOH. These four voltage levels are specified more specifically as follows.

VIH (high-level input voltage) is the minimum high input voltage to be recognized as logic 1.

VIL (low-level input voltage) is the maximum low input voltage to be recognized as logic 0.

VOH (high-level output voltage) is the minimum high output voltage when the output is logic 1.

VOL (low-level output voltage) is the maximum low output voltage when the output is logic 0.