What is the impact of interconnect resistance and capacitance (RC delay) in deep sub-micron technologies?

I think the main impact of RC delay is that in deep sub-micron nodes, wires have started to slow down the circuit more than the transistors. For example, in old technologies like 180nm, transistor switching time was the major delay, and wires were almost ignored. But in nodes like 28nm or 7nm, the transistors switch very fast, while the interconnects (the metal wires) become thinner and longer, which increases their resistance. Also, since the wires are placed very close to each other, the capacitance between them increases. Together, this RC effect makes signals take longer to travel. That’s why a long wire across the chip can delay signals more than several logic gates combined.

We usually notice that RC delay also limits scaling benefits. You can make transistors faster, but wires don’t scale as well. As we move to smaller nodes, interconnect pitch shrinks, which increases resistance and coupling capacitance. That makes global interconnects very slow and forces designers to use repeaters, shielding, or new materials like copper and low-k dielectrics