Layout Post Processing
Traditionally, the process of designing integrated circuits (ICs) involved converting specifications into physical layouts, verifying timing, and ensuring that the polygons met design rule-checking (DRC) standards. Once this was completed, the physical design was ready for fabrication. The data files for various layers were sent to a mask shop, where they were used to create masks. These masks were then sent to the fabrication facility, where the ICs were manufactured, marking the end of the design process.
In modern IC design, additional steps are required after the physical layout is created, a process referred to as layout post-processing. Layout post-processing involves making amendments and additions to the chip layout data to prepare it for mask production. This process can be broken down into three main steps:
Chip Finishing
This step involves adding custom designations and structures to improve the manufacturability of the layout. These customizations help ensure that the physical design can be manufactured effectively.
Producing a Reticle Layout
In this phase, a reticle layout is created, which includes test patterns and alignment marks. These elements are essential for the fabrication process and are used to ensure the accuracy of the final ICs.
Layout-to-Mask Preparation
This step involves enhancing the layout data with graphics operations and adjusting it to fit the requirements of mask production devices. It ensures that the layout data is ready for the mask-making process.
While the first two steps, chip finishing and producing a reticle layout, are not directly related to the physical design process, they are crucial for the overall IC fabrication process.
The third step, layout-to-mask preparation, may have a direct impact on the physical design. It involves several operations to enhance the optical resolution of the layout data. These operations are part of resolution enhancement techniques (RET) and are necessary for cutting-edge ICs with extremely small feature sizes. RET can impact physical design by introducing layout restrictions.
Main categories of RET operations
Distortion Corrections: These operations compensate for distortions that occur during the manufacturing process. For example, optical proximity correction (OPC) addresses image errors caused by diffraction effects. It adjusts mask openings to counteract these effects.
Reticle Enhancement: These operations aim to improve the manufacturability or resolution of the lithography process. Examples include phase-shift masks that use interference to enhance image resolution and double or multiple patterning, which splits dense patterns into interleaved patterns to increase feature density.
Double/multiple patterning introduces new layout constraints, as mask layers are assigned specific colors based on spacing requirements. These constraints must be considered by designers to avoid subsequent violations during decomposition.
It’s important to note that layout post-processing, including RET, is an evolving field that adapts to new technologies. Therefore, designers should stay informed about the latest developments in layout preparation and RET techniques through up-to-date literature and resources.