Pass-Transistor Logic (PTL), also known as transmission-gate logic, is based on the use of MOSFETs as switches rather than as inverters, Pass Transistor Logic involves nMOS or pMOS transistors to transfer the charge from one node of a circuit to another node under the control of MOS gate voltage.
An nMOS transistor is an almost perfect pass 0 and thus we say it passes a strong 0. However, the nMOS transistor is imperfect at passing a 1. The high voltage level is less than VDD. We say nMOS pass weak 1.
A pMOS transistor is an almost perfect pass 1 and thus we say it passes a strong 1. However, the pMOS transistor is imperfect at passing a 0. The high voltage level is less than VDD. We say pMOS pass weak 0.
If the Gate and Drain are both at VDD, the source can raise only up to one threshold below the gate. These are called threshold drops. Nmos pass up to Vdd-Vt and PMOS pass up to |Vtp|.
Pass transistor Logic Example.
Charge sharing is a serious problem in pre-charge circuits and must be carefully guarded against. This problem occurs when two capacitive nodes charged to different voltages are connected through a pass-transistor. When the pass transistor is turned on, it connects the two nodes, resulting in the redistribution of the charge on both nodes.
Capacitors C1 and C2 are in parallel when pass transistor P is conducting. This forces the voltages across C1 and C2 to be equal. If the two capacitors are charged to different initial voltages, charge sharing will occur when P turns on. Let the initial voltage and charge on C1 be V1 and Q1, and the initial voltage and charge on C2 be V2 and Q2. After the pass transistor turns on, the final charges on C1 and C2 are Q1f and Q2f, respectively, and both capacitors are charged to voltage Vf.
The initial charge balance equation is
Q1 + Q2 = C1V1 +C2V2
The final charge balance equation is
Q1f + Q2f = (C1 +C2)Vf
To find the final charge distribution, equate the charges before and after P turns on
C1V1 + C2V2 = (C1 +C2) Vf
A sneak path is created when two pass transistors are both ON at the same time and one is connected to VDD while the other is connected to GND.
Realize the following gates using Pass transistor logic
- 3-input NAND gate
- 2-input NOR gate
- 3-input XOR gate
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