How does transistor folding affect delay variation in standard cells?

The effect of folding on delay variation depends on the technology node. In older nodes like 180nm, a single wide transistor was fine because variation was less critical. But in deep sub-micron nodes like 7nm or 5nm, folding is almost necessary. It reduces mismatch caused by lithography and stress, so the cell becomes more reliable. For example, in FinFET-based cells, folding ensures balanced fins, which reduces delay variation across chips.

Folding is useful, but it also adds extra routing and parasitic capacitance. When we connect all the fingers together, the interconnect between them increases resistance and capacitance, which sometimes increases delay. For example, in a NAND gate layout, folding the pull-down NMOS can make the wiring longer, and this may add variation in delay compared to a single wide transistor.

Transistor folding helps reduce delay variation because it balances current flow and minimizes mismatch between fingers. For example, when you use multiple smaller transistors instead of one big one, the layout becomes more symmetrical. This symmetry makes timing more stable, especially in high-speed standard cells.