Soft check and Stamping Conflict error
Soft check and Stamping Conflict errors come into the Physical Verification of Layout.
What is a Soft check error?
Any two different nodes are connected with a high resistive path or connecting without any physical routing layer(Metals), it’s called a Soft check. Soft check errors come into ERC check, To understand the soft connection error, Let’s take one example. Suppose You have PMOS and want to connect their source with power(VDD). For PMOS we need an n+ tap to give ohmic contact to NWELL.
In the above Figure, N+ into NWELL is Connected with power, and on another side, with other N+ we are giving a connection to the device source. So instead of giving a direct connection to the source, we are giving a connection through NWELL(Hight resistive path), in this case in the ERC report we will get a Soft check error.
What is a Stamping Conflict error?
In the LVS Report file, the Stamping Conflict error will come. Any device without taps, floating NWELL, and floating substrate will consider a Stamping Conflict error as shown in the following figure.
