What is a Soft Check or a Stamping Conflict at LVS?
Soft Check or Stamping Conflict Error is a common error reported during LVS (Layout Versus Schematic) and ERC (Electrical Rule Check) verification. It occurs when two or more nets become connected through a high-resistance layer such as N-well, P-well, or substrate.
For a complete understanding of LVS verification, common LVS errors, debugging techniques, and physical verification flow, read our complete LVS guide:
👉 https://siliconvlsi.com/lvs/
What is a Soft Check Error?
A Soft Check identifies shorts between two or more signals that are connected through high-resistance materials such as:
- N-well
- P-well
- P-substrate
- Deep N-well
These connections may not be direct metal shorts, but they can still affect circuit functionality and reliability.
What is a Stamping Conflict Error?
A Stamping Conflict occurs when multiple nets attempt to assign different names or connectivity information to the same well or substrate region.
Since wells and substrates are resistive layers, LVS tools may be unable to determine which net should “stamp” or define the connectivity of that region, resulting in a stamping conflict error.
When Does a Soft Check or Stamping Conflict Occur?
Common situations include:
- Two or more nets connected through N-well or P-substrate.
- Floating N-well or floating substrate.
- Missing well taps.
- Missing power or ground connections.
- Two N-well regions connected through a well tap and metal connection.
- Different layout nodes connected through high-resistance layers.
How to Fix Soft Check and Stamping Conflict Errors?
The following methods are commonly used to resolve these errors:
- Verify all N-well and P-substrate connections.
- Ensure well taps are connected to the correct power and ground nets.
- Check for floating wells or floating substrates.
- Review LVS and ERC reports carefully.
- Verify connectivity between devices and taps.
- Ensure all well regions are stamped by the correct net.
Most LVS tools provide detailed reports that help engineers identify the exact location of the conflict and resolve it efficiently.
Difference Between Stamping Conflict and Sconnect Error
Although both errors are related to connectivity, they are different:
Stamping Conflict
- Related to well and substrate connectivity.
- Occurs when multiple nets attempt to stamp the same region.
- Commonly reported in LVS and ERC checks.
Sconnect Error
- Related to connectivity mismatches between layout and schematic.
- Indicates inconsistencies in electrical connections.
- Often reported during LVS comparison.
Both errors must be resolved before signoff and tapeout.
Example of a Stamping Conflict
[Insert your stamping conflict image here]A stamping conflict can occur when multiple well regions become electrically connected through high-resistance layers, causing the LVS tool to report ambiguity in connectivity assignment.
Learn More About LVS
This article covers Soft Checks and Stamping Conflicts, which are common LVS debugging topics.
For a complete understanding of LVS verification, signoff methodology, LVS flow, and debugging techniques, visit:
👉 https://siliconvlsi.com/lvs/
Related Articles
- LVS (Layout Versus Schematic) in VLSI
- Inputs Required for LVS
- DRC (Design Rule Check)
- Physical Verification in VLSI
- ERC (Electrical Rule Check)
Conclusion
Soft Check and Stamping Conflict errors are commonly encountered during LVS and ERC verification. These errors are typically associated with high-resistance layers such as N-well and substrate regions. Understanding the root cause of these errors and applying proper debugging techniques helps engineers achieve faster LVS closure and successful tapeout.
- LVS (Layout Versus Schematic)
- Inputs Required for LVS
- DRC (Design Rule Check)
- Physical Verification in VLSI
- ERC (Electrical Rule Check)
Frequently Asked Questions (FAQs)
What is a Soft Check in LVS?
A Soft Check is an LVS or ERC warning generated when two nets are connected through a high-resistance layer such as N-well or substrate.
What causes a Stamping Conflict?
A Stamping Conflict occurs when multiple nets attempt to stamp or define connectivity for the same well or substrate region.
How do you fix a Stamping Conflict?
Verify well taps, substrate connections, power connections, and review the LVS report to identify conflicting nets.
Is a Stamping Conflict an LVS error or ERC error?
It is commonly reported during LVS and ERC verification because it involves connectivity through resistive layers.